CXL: Advancing Coherent Connectivity


Delivering high-performance interoperable computational infrastructures is vital to meeting the exponential growth of global data for applications in Artificial Intelligence, Machine Learning, Analytics, Cloudification of the Network and Edge, and High-Performance Computing. CXL™ (Compute Express Link™), an open interconnect standard, delivers coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices to deliver optimized performance in evolving usage models. The CXL Consortium has released CXL specification 3.0, expanding on previous versions to increase scalability and optimize system-level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. In addition to memory pooling, CXL 3.0 enables memory sharing, which allows system designers to utilize machine clusters to address modern issues through memory constructs. The CXL 3.0 specification also introduces fabric capabilities beyond the traditional tree-based architectural structures of PCI Express® (PCIe®) and previous CXL iterations. This panel session will begin with an update from the Consortium, highlighting updates to the CXL specification and the new usage models enabled by CXL. An in-depth discussion from our panelists will explore the importance of delivering interoperable ecosystems, allowing enterprises and system architects to address modern challenges within the supercomputing community. Attendees will have an opportunity to ask the panel of experts questions about advancing their existing architectures and CXL implementations.

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