Overcoming SMBus limitations with I3C


With the growing trend for PCIe and CXL solutions, there is a need to improve the sideband management path as currently defined using SMBus. The newest SNIA SFF-TA-1009 specification for EDSFF PCIe devices released in January 2023 defined a method to allow I3C upgrade of the management SMBus/I2C bus. Other standards organizations, such as OCP and PCI SIG, are looking into adopting the same design. OCP and PCI‑SIG agreed that a backward-compatible upgrade of SMBus was required (see Composable Security Architectures call to action at OCP Global Summit 2021, PCI SIG agreed to this in 2020). 

We are presenting how important this upgrade is to solve the technical challenges that the new use cases create for SMBus architecture (example new use cases are MCTP protocol, SPDM-based attestation, telemetry reporting, or other asynchronous communications). We are showing how these challenges can be overcome by employing I3C-based solutions that have been designed from the very beginning with the new use cases in mind (the authors of this presentation co-authored the key specifications in this area: MIPI I3C, DMTF MCTP I3C Binding, I3C HUB design, NVMe-MI, EDSFF, and a newly proposed method to read VPD data over I3C). We are also showing how the I3C solution, which is backward-compatible with the legacy SMBus-only devices, actually improves operation of such legacy devices when they are attached to an I3C-capable system. 

This paper presents the experimental results that validate the solution, including advanced topics such as polling mode, and includes the conclusions coming from the electrical and topology analysis. Intel and Solidigm partnered to implement the first I3C solution using off-the-shelf components from Aspeed, Renesas, and Microchip. This collaboration generated the experimental results demonstrating how SMBus fails to deliver the necessary functions and the value that comes with I3C upgrade.

Janusz Jurski
Intel Corporation
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